1. Field of the Invention
This invention relates to integrated circuit design and, more particularly, to the layout of integrated circuits.
2. Description of the Related Art
Since the first semiconductor integrated circuit (IC) was built many years ago, semiconductor device geometries have been shrinking at a phenomenal rate. The reduction in device geometries may be driven by various factors. IC manufacturers may overcome their huge investment in the building and start-up of a fabrication facility (fab) using economies of scale. For example, the smaller a manufacturer can make an IC, the more ICs may be manufactured on a single semiconductor wafer. This concept translates to more dollars per wafer. Another factor that may be driving the reduction in device geometries is the demand for faster components. Generally speaking, as a device's critical dimensions such as the transistor physical gate width (which corresponds to the transistor's channel length) are reduced, the device becomes faster. Since there is an ever-increasing demand for faster microprocessors and related computer system components, the manufacturing process is driven to produce ever-smaller devices. Consistently controlling a transistor's channel length (and thus the physical gate width) is an important aspect for yielding high performance integrated circuits. However, as device geometries get smaller, it becomes more difficult to consistently control the transistor's channel length.
The manufacturing process involves many complex process steps. For example, one of the manufacturing process steps is photolithography. In the photolithography step, the IC devices and connections are patterned onto the wafer in various steps using light sources, optics, photoresist, and mask sets. Another manufacturing process step includes one or more etch steps. Etching includes removing or etching unwanted portions or layers of the IC or photoresist using various etching techniques. Due to limitations in various process steps such as the photolithography process and the etching process, for example, the ability to pattern and etch the devices uniformly becomes more difficult as the device geometries shrink. This may result in difficulty predicting the resulting critical dimensions of devices. This may be especially true when patterning and etching polycrystalline (poly) silicon.
Depending upon how densely the devices are packed together may determine how closely the patterned dimensions compare to the dimensions as specified and drawn. A given process may yield a given poly gate width for devices having one poly pitch. However, when the same process is used on a group of devices with a different poly pitch, that same process may yield a different gate width. This same phenomenon may be observed for other lines patterned onto the wafer. Stated differently, the finished line widths may vary depending on the line-to-line pitch. This variance is sometimes referred to as across chip line-width variation (ACLV).
To overcome this unpredictability, IC designers may group devices in a particular area (or an entire chip) such that the pitch between polysilicon gates is substantially the same for all the devices in that area (or chip). Designers may use some predetermined ACLV guidelines to control the line widths, etc. For example, by making the pitch substantially the same for the devices in the area, the line widths may be more closely predicted and controlled. Controlling the line widths may be of particularly interest for devices that have gates with critical dimensions. However, enforcing the ACLV guidelines may be challenging due to fringe effects that may be caused by any changes in the density of the polysilicon near the edges of the ACLV controlled areas.